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| TECHNICAL DATA OCTAL BUFFER/LINE DRIVE; 3-STATE The KK74LV240 is a low-voltage Si-gate CMOS device and is pin and function compatible with KK74HC/HCT240. The KK74LV240 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The KK74LV240 is identical to the KK74LV244 but has inverting outputs. * * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 3.6 V Low Input Current: 1.0 A, 0.1 at = 25 Output Current: 8 mA at VCC = 3.0 V High Noise Immunity Characteristic of CMOS Devices KK74LV240 N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION KK74LV240N KK74LV240DW Plastic SOIC TA = -40 to 125 C for all packages LOGIC DIAGRAM 1A0 1A1 1A2 1A3 2A0 2A1 2 4 6 8 11 13 18 16 14 12 9 7 5 3 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y0 2Y1 PIN ASSIGNMENT 1OE 1A0 2Y3 1A1 INVERTING OUTPUTS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 2OE 1Y0 2A3 1Y1 2A2 1Y2 2A1 1Y3 2A0 DATA INPUTS 2Y2 1A2 2Y1 1A3 2Y0 GND 2A0 15 2A1 17 OUTPUT ENABLES 1OE 2OE 1 19 FUNCTION TABLE Input nOE L PIN 20=VCC PIN 10 = GND Output nAn L H X nYn H L Z L H H= high level L = low level X = don't care Z = high impedance 1 KK74LV240 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD 1 2 Parameter DC supply voltage DC Input diode current DC Output diode current DC Output source or sink current DC VCC current DC GND current Power dissipation per package: * Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds 4 Value -0.5 to +5.0 20 50 35 70 70 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, tf DC Supply Voltage Input Voltage Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 3.6 VCC VCC +125 1000 700 500 400 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV240 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol VIH Parameter HIGH level input voltage conditions VCC V 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 VI = VIH or VIL IO = -50 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 * 1.2 * * 25C min 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 0.1 0.5 Guaranteed Limit -40C to 85C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 1.0 5 125C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 1.0 10 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -8 m VOL LOW level output voltage VI = VIH or VIL IO = 50 V V VI = VIH or VIL IO = 8 m II IOZ Input current VI = VCC or 0 V Three state leakage 3-state outputs current VI (01,19) = VIH VO =VCC or 0 V Supply current VI =VCC or 0 V IO = 0 V ICC - 8.0 - 80 - 160 * VCC = 3.3 0.3 V 3 KK74LV240 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns) Test Symbol Parameter conditions VCC V 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 3.0 VI = 0 V or VCC 25C 100 24 15 140 30 20 140 32 20 60 16 10 7.0 50 Guaranteed Limit -40C to 85C max 125 30 19 175 35 24 175 40 25 75 20 13 7.0 125C min max 150 36 23 210 41 28 210 48 30 90 24 15 7.0 ns Unit min max min tPHL, tPLH Propagation delay , 1An to VI = 0 V or VCC 1Yn, 2An to 2Yn Figure 1 and 3 tPHZ tPLZ Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 tPZH tPZL Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 tTHL, tTLH Output Transition Time, Any Output CI CPD Input capacitance Power dissipation capacitance (per one channel) VI = 0 V or VCC Figure 1 and 3 ns ns ns pF pF * VCC = 3.3 0.3 V tr 1An or 2An 10% 90% 50% tf VCC GND t PHL 1OE or 2OE t PZL 1Yn or 2Yn 50% VCC t PLZ 50% GND VCC tPLH 1Yn or 2Yn t THL 90% 50% 10% t PZH t PHZ 50% VOL VOH GND t TLH 1Yn or 2Yn Figure 1. Switching Waveforms TEST POINT DEVICE UNDER TEST Figure 2. Switching Waveforms TEST POINT 1k CL * OUTPUT * CL DEVICE UNDER TEST OUTPUT Connect to V CC when testing tPLZ and tPZL Connect to GND when testing tPHZ and tPZH * Includes all probe and jig capacitance Figure 3. Test Circuit * Includes all probe and jig capacitance Figure 4. Test Circuit 4 KK74LV240 N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H H J M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 Dimension, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0 0.1 0.23 10 0.25 8 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SEATING PLANE J F M G H J K M P R NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 5 |
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